Introduction To Vhdl For Fpga And Asic Design

Last updated 9/2020
MP4 | Video: h264, 1280×720 | Audio: AAC, 44.1 KHz
Language: English | Size: 1.66 GB | Duration: 9h 3m

From VHDL basics to sophisticated testbench coding

What you’ll learn
Practical FPGA and ASIC RTL design using VHDL
Requirements
Basic understanding of electronics and logic
Description
Twelve lectures, starting from the basics of VHDL, including the entity, architecture, and process. Explanations of the difference in sequential and concurrent VHDL. Discussions of good synchronous design methodology. Demonstrations on how to use the Altera Modelsim and Xilinx Vivado simulators. Six lab projects for hands-on experience, with the instructor showing how he would have done each lab.

Overview

Section 1: Introduction to VHDL , a first look

Lecture 1 Why VHDL

Lecture 2 First VHDL design

Lecture 3 Acquiring a VHDL simulator

Lecture 4 Download and install Altera Modelsim

Lecture 5 Download and install Xilinx Vivado Simulator

Lecture 6 Vivado Simulator Demonstration

Lecture 7 Modelsim (Altera Quartus) Demonstration

Lecture 8 Alternate Lab 1 Solution using Vivado

Section 2: Concurrent and Sequential VHDL

Lecture 9 The VHDL Process

Lecture 10 Concurrent and Sequential Statements

Lecture 11 VHDL Hierarchy

Lecture 12 Testbench Demo with Vivado

Lecture 13 Testbench Demo with Modesim

Section 3: RTL

Lecture 14 Understanding the Flip-Flop

Lecture 15 Synchronous Design Methodolgy

Lecture 16 RTL Styles

Section 4: VHDL Types

Lecture 17 Multivalue logic (std_logic)

Lecture 18 Logic Arrays and Variables

Lecture 19 State Machines

Section 5: VHDL Operators

Lecture 20 VHDL logical and relational operators

Lecture 21 Math Operators

Lecture 22 Functions, Procedures, and Packages

Section 6: Verification

Lecture 23 Verification

Lecture 24 Self Checking Testbenches

Beginner FPGA or ASIC designer

---

Password/解压密码www.tbtos.com